1. Field of Invention
The present invention relates to a method for manufacturing integrated circuit (IC). More particularly, the present invention relates to a method for manufacturing metal-oxide-semiconductor (MOS) device.
2. Description of Related Art
As techniques for fabricating semiconductor devices continues to improve, silicon wafer having a larger size and MOS device having a smaller line width are now being manufactured. Consequently, more devices and circuits can be packed inside a single silicon chip and hence the cost of production is lowered considerably. However, the miniaturization of semiconductor devices is accompanied by a host of problems that must be tackled. For example, as line width of a device shrinks, channel length of a MOS device will reduce leading to short channel effects.
Short channel effects are detrimental to the normal operation of a MOS device. As the channel length is shortened, the depletion region around the source/drain of a MOS device will begin to encroach upon the channel region so that the subthreshold current within the channel may increase considerably. Under these circumstances, the MOS device will be in an "ON" or "OFF" state even when no control voltage is applied to the gate terminal of the MOS device. Hence, the intended function of the MOS device is completely lost.
Furthermore, as the length of a channel is reduced, hot electrons can strongly affect the operation of a MOS transistor. Supposing that the source voltage applied to a MOS device remains unchanged, a shorter channel will tend to increase the strength of lateral electric field across the channel. Therefore, some electrons having an energy level higher than that at the thermal equilibrium level, the so-called hot electrons, will be accelerated by the strong electric field to form a large substrate current. The substrate current may interfere with the normal current flowing inside the channel. Occasionally, the substrate current may be large enough to cause the breakdown of MOS device.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps according to a conventional method for producing a MOS device whose source/drain regions has a lightly doped drain (LDD) structure.
First, as shown in FIG. 1A, a substrate 100 having an isolation region 102 and a gate 110 thereon is provided. Thereafter, using the isolation region 102 and the gate 110 as a first mask, a first ion implantation 116 is carried out implanting phosphorus ions having a concentration of about 10.sup.13 /cm.sup.2 into the substrate 100 to form lightly doped source/drain regions 130. Next, as shown in FIG. 1B, a silicon dioxide layer 120 is formed over the substrate 100 using, for example, a chemical vapor deposition (CVD) method. Thereafter, the silicon dioxide layer 120 is annealed by heating to a temperature of between 900.degree. C. to 1000.degree. C.
Subsequently, as shown in FIG. 1C, an anisotropic etching operation is carried out to form spacers 120a. A dry etching method is used to remove a large portion of the silicon dioxide layer 120 above the substrate 100. Because the silicon dioxide layer 120 on the sidewalls 109 of the gate 110 is particularly thick, a portion of the silicon dioxide layer will still adhere to the sidewalls 109 of the gate 110 after the anisotropic etching operation.
Finally, as shown in FIG. 1D, a second ion implantation 126 is carried out using the spacer-lined gate 110 and the isolation region 102 as a second mask. In the second implantation, phosphorus ions having a concentration of about 10.sup.15 /cm.sup.2 are implanted into the substrate 100 to form a heavily doped source/drain region 150 inside the lightly doped source/drain region 130.
However, in the process of manufacturing a MOS device, some problems frequently appear especially when the line width of the MOS device is reduced below 0.25 .mu.m. Normally, a self-aligned silicide (Salicide) process will be carried out to form a metal suicide layer over the source/drain region and the gate for increasing the electrical conductivity there. In the salicide process, for example, metal such as titanium is deposited over the source/drain regions and the gates followed by a rapid heating operation. When the level of integration for transistors increases, the titanium silicide layer above the source/drain region may punch through the junction between the LDD structure and the source/drain region. Hence, the source/drain region may contact the semiconductor substrate directly resulting in failure of transistor devices.
Furthermore, the punch-through margin when ions are implanted into the source/drain region will be closer to the substrate as the level of integration is increased. This can substantially increase the possibility of current leak from a transistor device.
In light of the foregoing, there is a need to improve the method for manufacturing a MOS device.